When performing high frequency parallel to serial conversions, it is necessary to load parallel data into a shift register without corrupting the data. One problem that arises is the timing associated with loading the parallel data into the shift register. Typically, the parallel data is received at a known frequency that is related to the frequency of the serial data produced. For example, in an eight bit parallel to serial converter, the frequency of the serial data is eight times that of the parallel data. However, although the frequency of the incoming parallel data is known, its phase relationship with respect to a timing mechanism for clocking the parallel data into the shift register is not known. Due to this unknown phase relationship, the parallel data may be received by the shift register at the same instant that the parallel data is changing state. If that occurs, the data may be corrupted. Therefore, a need has arisen for a method and apparatus for synchronizing external data to an internal timing signal.